As the industry’s leading semiconductor manufacturer, Taiwan Semiconductor Manufacturing Company (TSMC) has just shared more details about the next-generation process node. During the 2021 online technical seminar earlier today, Dr. YJ Mii, senior vice president of TSMC R&D, introduced the latest plans for the N6, N5, N4, and N3 process nodes one after another. In addition to the density of the wafer process, we also learned about the capacity and launch schedule of different manufacturing nodes.
First of all, Mi Yujie emphasized that TSMC has substantially increased R&D expenditure and the number of employees in 2020, and reached a record level. And since the 7nm process was first introduced in 2017, the shipment of related chips has exceeded 1 billion.
Facts have proved that the 7nm node has a crucial impact on AMD. The latter’s CPU and GPU are one of the first products to adopt the N7 process and have helped it engage in a fierce market battle with rival Intel.
As for the N3 process node, TSMC claims that compared with the N5 generation, 3nm will bring better performance and power consumption. The company has already started mass production of 5nm chips, followed by N4.
Mi Yujie said that the N4 process will continue to shrink the chip size by 6% while bringing further improvements in power consumption and performance. For example, compared with FinFET transistors (red line in the figure below), Nanosheet (blue line in the figure below) can achieve a more stringent threshold voltage (Vt) control.
It is reported that Vt specifically refers to the minimum voltage required for the operation of a semiconductor circuit. Even the slightest change will restrict the chip design and cause performance degradation. Fortunately, TSMC managed to achieve a 15% lead.
Although there is no clear link between the R&D progress in this area and the 2nm process, we are still full of expectations for the subsequent process development of TSMC.
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