The latest generation leap in working memory can finally be made. The specifications for the DDR5 standard have been finalized and have now been officially published – so you can start with high capacities and a lot of speed.
The responsible industrial consortium JEDEC has worked intensively on the details for a long time. And that will make itself felt in practice. For example, compared to the predecessor DDR4, which started six years ago, the data transfer rate per pin has been doubled. In addition, the capacity to build storage devices has quadrupled. By reducing the operating voltage, the new storage should be able to be used in more compact devices, since less waste heat is also produced.
Above all, the standard capacity increases are extremely important for the system manufacturers. Because only two modules can be addressed per memory channel – unless you use additional, complex subsystems such as LRDIMMs or buffered solutions, which, however, slow down the performance. With DDR5, much more memory can now be addressed at maximum speed.
It starts next year
The first DDR5 modules will probably be used in practice in the course of the coming year, but the first samples have been around for some time. First, servers and premium PCs will be equipped with the new storage technology, all other systems will follow. Initially, the manufacturers will offer chips with 8 and 16-gigabit capacity, which coincides with the DDR4 products.
However, it can be assumed that additional capacities will be made available very quickly. The standard also provides RAM dies with 24, 32, and 64 gigabits. This, of course, has an impact on the maximum DIMM capacities: The largest DDR4 bars with 256 gigabytes can be obtained from servers. DDR5 enables four times – one terabyte. And since twice as many memory banks can be used, up to eight times as much RAM can be installed per computer.
The DIMMs themselves won’t change much. The standard provides the same sizes. The pin row also looks the same. DDR5 DIMMs only have a slightly offset notch, so that it is ensured that the memory latches are only inserted in the correct sockets.
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